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2 IP Cores for
XILINX and ALTERA FPGAs / CPLDs: |
2.1 VHDL IP Core AES for
XILINX PFGAs: |
Optimized IP Core
to perform the AES algorithm in several of the XILINX FPGAs. Supports
AES-128, AES-192 and AES-256 |
2.2 VHDL IP Core TDES for
XILINX / ALTERA FPGAs / CPLDs: |
Optimized IP Core
to perform the TDES/DES algorithm in several of the XILINX and ALTERA
FPGAs. Supports AES-128, AES-192 and AES-256 |
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3 Generic Crypto
Modules written in C/C++ Language: |
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3.1
Standard DES/TDES Module "TDES":
Standard TDES module written in a bit operating style.
Extremely fast as a result of data processing in processor registers
wherever possible. Compatible to standard DES if all 3 keys are
identical |
3.2 Standard RSA Module
"RSA:
Standard RSA module written in a bit operating style.
Extremely fast as a result of data processing in processor registers
wherever possible |
3.3 Standard ENIGMA Module
"ENIGMA":
Standard ENIGMA module written in a bit operating
style.
Extremely fast as a result of data processing in processor registers
wherever possible.
Compatible with the "-x"-option of vi under UNIX including
the hidden feature "shuffle" |
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